Exams
| Exam | Time | Info |
|---|---|---|
| Quiz | Tues., Sep. 29 at 7 PM Pacific | Info |
| Midterm | Tues, Oct. 27 at 7 PM Pacific | Info |
| Final | Sat., Dec. 12 at 2:00 PM Pacific | Info |
Lectures
| Week | Lecture - Tuesday | Lab - Wednesday/Friday | Lecture - Thursday |
|---|---|---|---|
| 1 (8/24-8/28) |
Course overview, embedded systems, computer organization [ PDF Complete ] [ Day 1 Survey ] [ Watch this video BEFORE you come to Lecture 2 ] |
Lab 0: Installing the Arduino Toolchain (Linux tutorial, software installation) |
Basic circuit analysis (voltage, current, Ohm's law) [ PDF Notes ] [ PDF Complete ] |
| 2 (8/31-9/4) |
Transistors, Digital logic, combinational and sequential circuits [ PDF Notes ] [ PDF Complete ] |
Lab 1 - Electronic circuits (exploration of KVL/KCL/Ohm's laws) |
Boolean Algebra (Single-variable theorems) Combinational and sequential circuits [ PDF Notes ] [ PDF Complete ] |
| 3 (9/7-9/11) |
Number systems, binary, hexadecimal, character codes [ PDF Notes ] [ PDF Complete ] |
Lab 2 - Oscilloscopes, combination gate network, delays |
Microcontollers 1 (bitwise operations) [ PDF Notes ] [ PDF Complete ] |
| 4 (9/14-9/18) |
Microcontrollers 2 (digital I/O) [ PDF Notes ] [ PDF Complete ] |
Lab 3: Digital I/O lab with Arduinos |
Microcontroller 3 (advanced bit fiddling) LCDs and parallel interfaces [ PDF Notes ] [ PDF Complete ] |
| 5 (9/21-9/25) |
State Machines [ PDF Notes ] [ PDF Complete ] |
Lab 4: LCDs |
Interrupts [ PDF Notes ] [ PDF Complete ] |
| 6 (9/28-10/2) |
Combinational logic design 1 (Minterms/maxterms) [ PDF Notes ] [ PDF Complete ] |
Lab 5: Timers |
Combinational logic design 2 (Boolean Algebra, Karnaugh maps) [ PDF Notes (2025) ] [ PDF Complete (2025) ] [ PDF Notes (2024) ] [ PDF Complete (2024) ] |
| 7 (10/5-10/9) |
Combinational logic design 3 (More Karnaugh maps) [ PDF Notes ] [ PDF Complete ] |
Fall Break |
|
| 8 (10/12-10/16) |
Combinational logic design 4 (Components: Decoders and Muxes) [ PDF Notes ] [ PDF Complete ] |
Lab 6: Rotary Encoders |
Muxes [ PDF Notes ] [ PDF Complete ] |
| 9 (10/19-10/23) |
Signed Number Systems [ PDF Notes ] [ PDF Complete ] |
Lab 7: ADC/PWM |
Adders [ PDF Notes ] [ PDF Complete ] |
| 10 (10/26-10/30) |
Sequential logic 1 (latches, FFs and registers) [ PDF Notes ] [ PDF Complete ] |
Lab 8: Hardware Datapath Components |
Sequential logic 2 (latches, FFs and registers) [ PDF Notes ] [ PDF Complete ] |
| 11 (11/2-11/6) |
Hardware State Machines (1) [ PDF Notes ] [ PDF Complete ] |
Project |
Hardware State Machines (2) [ PDF Notes ] [ PDF Complete ] |
| 12 (11/9-11/13) |
Veteran's Day Holiday |
Hardware components (ALUs, registers, instruction cycle) [ PDF Notes ] [ PDF Complete ] |
|
| 13 (11/16-11/20) |
Processor Organization (Design of CPU) [ PDF Notes ] [ PDF Complete ] |
Project work (checkpoint 1 due) |
Processor Organization (Design of CPU) [ PDF Notes ] [ PDF Complete ] |
| 14 (11/23-11/27) |
Performance [ PDF Notes ] [ PDF Complete ] |
Thanksgiving Holiday |
|
| 15 (11/30-12/4) |
Memory/FPGAs [ PDF Notes ] [ PDF Complete ] |
Project Demos |
Interfacing (voltage and current capabilities) Review [ PDF Notes ] [ PDF Complete ] [ Review ] |
