# EE109 – Fall 2022: Introduction to Embedded Systems

## Final Info

### What, When and Where

Sat. May. 7 at 2 p.m.

Location

• All sections: SGM 123
• OSAS (1.5x) accommodations: SGM 101

The test will be taken via pen/paper. Please bring:

• A pen/pencil. (If using pencil please ensure your write darkly as we will scan the exams for grading and if we cannot read what you've written we will not be able to award points)
• A calculator.

### Topics

The exam is cumulative. So topics from midterm 1 will appear on the final exam, but will be focused on the applications from the second half of the semester. So you still need to know fundamental concepts (e.g. binary representation, implementing combinational logic functions with minterms, Boolean Algebra, Arduino programming basics and digital I/O, etc.). But, those topics will likely be tested in the context of what we've covered since the midterm. A more detailed list is given below:

#### Unit 8

• K-Maps (up to 4 variables, Don't cares, etc.)
• Implementing an arbitrary combinational function by converting a word description to a truth table and then implementing the circuit using K-Maps

#### Unit 9

• Decoder operation and building larger decoders from smaller ones.
• Mux operation and building larger muxes from smaller ones.
• Basic operation of tri-state gates

#### Unit 10

• Interrupts and ISRs
• Enabling with local and global interrupt enable bits
• ISRs
• Importance of the volatile keyword

#### Unit 11

• Signed number systems (2's complement)
• Addition and Subtraction in unsigned and 2's complement
• Overflow

#### Unit 12

• Adders (half and full) and their implementation
• Connecting multiple adders to compute a particular problem

#### Unit 13

• How a latch works
• Difference between latches (level-sensitive) and flip-flops (edge-sensitive)
• Given a circuit, draw the waveform for various signals in the design
• Initializing flip-flops (Using CLR and SET/PRE with the reset signal)
• Registers and registers with an enable (and their implementation)
• Operation of synchronous counters (with count enables, parallel/data load enables, reset, etc.)

#### Unit 14

• Rules for correctness of a state diagram (mutually exclusive but all inclusive transition conditions)
• Relationship of state diagram in regard to number of flip-flops, number of transitions from a state, etc.
• Designing a state machine circuit from a state diagram (1-hot design process)
• How to implement the initial state using reset and the CLR and SET/PRE inputs of the flip-flops

#### Unit 15

• General HW components inside a processor (registers, ALU, PC, etc.) and their responsibilities/usage
• Understand the operation and construction of various hardware components including wide muxes and ALUs
• Understand how to place muxes to build a simple datapath to accomplish certain operations.
• Given a datapath that we provide, derive the control logic signals (i.e. mux selects, enables, etc.) by generating a truth table for their necessary values.

#### Unit 16

• Basic kinds of instructions (arithmetic, data transfer, and control)
• Understand translation to machine code
• Understand basic datapath of a processor (ALU, register selection via muxes, etc.)

#### Unit 17

• Understand latency vs. throughput
• Understand basic concept of caching
• Understand basic concept of pipelining and how it affects throughput, clock rate, etc.

#### Unit 18

• Understand the difference between an ASIC and FPGA
• Understand how a memory can be used to implement any arbitrary combinational function by finding the necessary dimensions and contents of the memory
• Understand how to map a desired digital logic circuit to a Configurable Logic Block(s)

#### Appendix C - Timers

• General operation of a timer interrupt
• Be able to calculate a prescalar and modulus (max) count to generate an interrupt every n seconds
• Write a timer ISR to perform some task or generate a signal of interest

#### Appendix D - Serial

• Understand what baud rate is and what is meant by "asynchronous" communication

### Units NOT Covered in Fall 2021 and NOT tested

#### Unit 19

• Voltage level compatibility (VOL, VIL, VOH, VIH)
• Current requirements (IOL, IIL, IOH, IIH)
• Given some of these parameters, determine if devices are compatible for connection or how many devices can be connected

### Style

The exam will have some general short answer/fill in the blank question, and the rest will focus more on ability to apply knowledge through problems similar to your homeworks but requiring the use of 1 or more concepts that demonstrate understanding. You should know the material and procedures for solving problems well enough that you can quickly produce solutions once you identify the procedure to apply. If you spend unnecessary time trying to recall what procedure applies and how to perform that procedure you will likely run out of time.

### Ways to Prepare

• Study the slides
• For units 8, 11, 12, 13, 14, and 15 the Vahid textbook has review problems.
• For the others review your slides, homeworks, and labs.

### Samples

Here are some sample problems from past (related) exams. If a topic above is not represented in the practice exams below, you are still responsible for questions on that topic (i.e. there can/will be questions on the topics above that do not have corresponding practice problems in the exams below). However, most of the design-based problems you will see on the exam are represented in the practice exams below. Be sure to go over the topic list above and ensure you are ready. Most exams use the encoded method of state machine design, while we have focus on 1-hot, and will do so on the final.