EE 560 - Summer 2025 Digital Systems Design

Lectures

It is recommended that students take notes and actively participate during class meetings. Before class meetings, it is helpful to review relevant slide deck. Slides are in the shared Google Folder.

Exams

Exam Time Info
MT Wed, July 2 at 3 PM Pacific Info
Final Tues. July 22 at 1:00 PM Pacific Info

Lectures

Week Lecture - Tuesday Lab - Wednesday/Friday Lecture - Thursday
1
(5/20-5/22)
Semester has NOT started
[Slides]
Tools, VHDL, and Vivado; Parity Generator; Special Counter; Yards-Feet-Inches Course Overview
Gated Clocking
CAM
[Slides]
2
(5/27-5/29)
5-Stage CPU with BRAM
[Slides]
Gray Code Counter; Divider with Cache; Chipscope; UART Assistant FIFO with BRAM
[Slides]
3
(6/3-6/5)
Clk Skew
Timing Analysis
Wave Pipelining
[Slides]
CPU with BRAMs; FIFO with BRAMs (tentative) Tomasulo (Part 1-2)
[Slides]
4
(6/10-6/12)
Tomasulo (Part 3a)
[Slides]
Tomasulo, OoO Processor - (Front-end Components) Tomasulo (Part 3b)
[Slides]
5
(6/17-6/19)
Chip Multiprocessors (CMP)
[Slides]
Tomasulo, OoO Processor - (Back-end Components); AXI Juneteenth Holiday
(May have a recording to watch)
[Slides]
6
(6/23-6/25)
Chip Multiprocessors (CMP)
Barrel Shifters
Rotating Prioritizers
[Slides]
(Lab) CMP Non-linear Pipelines
Burst order
PCIe (Part 1)
[Slides]
7
(7/1-7/3)
PCIe (Part 2)
Midterm Review
(Lab) PCIe
[Slides]
Midterm PCIe (Part 2 / 3)
[Slides]
8
(7/8-7/10)
GPGPU (Part 1)
[Slides]
PCIe (Synthesis); GPGPU GPGPU (Part 2)
[Slides]
9
(7/15-7/17)
SRAM and DRAM
[Slides]
Demos SRAM, DRAM, DFT
Review
[Slides]
10
(7/22)
Final Exam
[Slides]
N/A No lecture (Semester is over)
[Slides]