EE 560 - Summer 2025 Digital Systems Design

Week 8 - GPGPU

Procedure

See subfolder Labs/Lab08/.

For this assignment, you will need to complete the several SIMT assembly exercise files to then run on a 1 SM (with 8 HW warps) and 8 SPs (8T/warp). You will simulate your design using Vivado (not Questasim).

Prelab

Review the GPGPU Lecture slides, especially the SIMT programming lecture and corresponding recordings on D2L.

Procedure

  1. Download and extract the .zip file with the lab materials from the shared folder.
  2. The setup and process is provided in the ee560-gpgpu-lab-2024.pdf file. It includes instructions for setting up Perl AND Python which you will need to “compile/assemble” your SIMT code.
  3. You can open the Xilinx project which is located in the syn subfolder. The source files you need to edit are in src/asm-mem/ICache_init.
  4. Use the procedure outlined in that document to update, compile, and test three exercises via simulation first. It is important that you do not rely too much on your lab partner. It may be best for each of you to arrive at the three .asm files independently. This will help you in your final exam!
  5. Note: For the drawing programs you can use the default memory file: MEM_init.txt, but for the matrix multiply (16x16 or 8x4), use MEM_init_a_1_digit_random_matrix.txt.
  6. Currently, we do NOT require synthesis and demoing on the FPGA. So simulation will suffice.

Submission

submit -user ee560 -tag GPGPU_circle circle_drawing_15x15.asm names.txt
submit -user ee560 -tag GPGPU_diamond diamond_drawing_15x15.asm names.txt
submit -user ee560 -tag GPGPU_matrix matrix_mult_8x4.asm TM_8x4_init.txt names.txt