EE 560 - Summer 2024 Digital Systems Design

Week 7 - PCIe

Procedure

See subfolder Labs/Lab07/.

For this assignment, you will need to complete the 6 exercise files to finish the design of a 2 lane PCIe link. Not only will you simulate your design, but also synthesize and test it with the uartAssistant file I/O. You will finish with some review questions (posted in the shared folder).

Prelab

Review the PCIe Lecture slides and lecture recordings on D2L.

Procedure

1. Download and extract the .zip file with the lab materials from the shared folder.
2. Follow the specific procedure in the PCIe Lab slides that are posted in the lab shared folder to open and update the project in Vivado.
3. Complete the exercise code files and simulate your design, verifying that they produce the correct results. It would be best at this point to skim the review questions posted in the shared folder since some of them ask for screen shots of simulation results and you can capture those as you go.
4. Synthesize your design and download the .bit file to the FPGA. Follow the instructions in the lab slides to use the uartAssistant and .ark file to verify the design.
5. Then add the ILAs back in the code, set up the triggers, and use ChipScope to capture the specified traces. Again, take appropriate screen shots for your review questions.

Submission

• Online Submission: From your src/des/ folder copy over the following files to your SCF account:
  • pcie_phy_8b10b_exercise.v
  • PHY_rx_exercise.v
  • PHY_rx_lane_exercise.v
  • decoder_10b_8b_BRAM_exercise.v
  • elastic_buffer_exercise.v
  • deskew_fifo_exercise.v
  • names.txt
• You can run the following submission command (which is all one line) or the individual submission commands below (as long as you submit all 6 files).

submit -user ee560 -tag PCIe pcie_phy_8b10b_exercise.v PHY_rx_exercise.v PHY_rx_lane_exercise.v decoder_10b_8b_BRAM_exercise.v elastic_buffer_exercise.v deskew_fifo_exercise.v names.txt

or

submit -user ee560 -tag PCIe pcie_phy_8b10b_exercise.v names.txt
submit -user ee560 -tag PCIe PHY_rx_exercise.v
submit -user ee560 -tag PCIe PHY_rx_lane_exercise.v
submit -user ee560 -tag PCIe decoder_10b_8b_BRAM_exercise.v
submit -user ee560 -tag PCIe elastic_buffer_exercise.v
submit -user ee560 -tag PCIe deskew_fifo_exercise.v

• Synthesis Demo: This lab requires a demo using the uartAssistant and included .ark file.

• Review Questions: Complete the review questions in the shared folder (both in .docx or PDF format) and submit them on Gradescope