EE 560 - Summer 2025 Digital Systems Design

Week 6 - Code Coverage

See subfolder Labs/Lab06b-Code-Coverage.

Overview

In this lab, we provide a working number lock state machine design and have you complete the testcases in the testbench and run code coverage to ensure your tests are comprehensive and cover all the statements and conditions in the design.

Procedure

Part 0

1. Download and extract the .zip file containing the source code files:
   • src/des/number_lock.vhd (complete)
   • src/tb/number_lock_tb.vhd (to be completed by you)
   • sim/coverage.do (to be completed)
2. Understand the design and given portion of the test bench provided.
3. Note that to enable coverage, the compilation command must include the -cover <flags> option/argument
   • vcom -cover bcesxf <design_filename.vhd> to vcom
4. Similarly, the simulation command must include the -coverage option:
   • vsim -coverage work.<testbench_top_entity_name>

Part 1: Running Modelsim Code Coverage

1. Update the sim/coverage.do file in an editor to include the necessary options/flags shown aboe in Part 0.
2. Invoke Questasim and use File..Change Directory to the sim folder of this design.
3. Compile and run the simulation by executing: do coverage.do

Part2: Analyzing the Code Coverage result – Statement Coverage

• We want you to analyze only the Statements and Branches Coverage for the number lock design to achieve 100% coverage. Using the testbench provided will NOT achieve that. Refer to the corresponding writeup for how to read and access the coverage results.

Part3: Add TestCases

• Go back to the testbench and add test cases at the bottom of the stim_num_lock process.
• Note that since we want to run all our testcases sequentially, we have provided a get_to_initial procedure (subroutine). Without it, one test might end in a particular state and you’d need to enter commands to get back to the initial state to start your next testcase. Instead, just call the get_to_initial procedure as you see at the top of the second test case provided.
• Try to be systematic and not haphazard so that it is easy to read your test cases in the given order and have confidence how it is progressing through the possible input cases.
• Compile and simulate after the first one or two test cases that you add to make sure your approach is working. You can then likely copy/paste significant portions of code (or create other procedures) to make subsequent test cases fast to write.
• Continue this iterative process of writing testcases, compiling, and simulating until you achieve 100% statement, branch, and condition coverage.

Part4: Exploring DeadCode

Once you have achieved 100% coverage, take a moment to uncomment the lines 51, 99, 100 (or potentially slightly differt) and then COMMENT line 52.

• Line 51: -- if (u = '1' and z = '0' and zbar = '1') then
  • Adding this line back in should reduce your branch/expression coverage since you cannot independently cause z='0' to be false while zbar='1' is true. In a real desing, the inability to toggle a condition should help your recognize redundancy.
• Line 99: -- when BAD =>
• Line 100: -- state <= INITIAL;
  • Adding these two lines gives an explicit BAD state case and make when NULL => unreachable and your statement coverage to drop.

You should see full coverage except for these lines:

And the final Instance percentages should be:

Submission

• Online Submission: Submit the following files
  • number_lock_tb.vhd (from src/tb folder)
  • names.txt

submit -user ee560 -tag code-cov number_lock_tb.vhd names.txt

NOTE:* We are NOT running automated tests. This submission is just to collect and review your work. So your submission will automatically trigger the Congratulations result. The VAST MAJORITY of your points will come form your Demo (see below).

• Demo run your simulation and show your TA your coverage statistics which should be 100% except for the reductions due to uncommenting the lines we indicated.