EE 560 - Summer 2025 Digital Systems Design

Week 5

See subfolder Labs/Lab05-AXI.

Overview

This lab introduces you to the AXI (Advanced eXtensible Interface) bus protocol specification from ARM. It allows initiators (like processors or DMA engines) to communicate with responders (like memory or I/O modules). Our design will connect 4 initiators with 4 responders via a switched network which raises the potential of out-of-order handling of read and write requests. The AXI protocol places some requirements on how this must be handled and you will learn about these and implement portions in the RTL.

Prelab

Your TA will review requisite information about the AXI standard. Please carefully re-read and study the slides posted in the shared folder.

Procedure

Complete the RTL code for the design as described in the following tasks.

Task 1a - Initiator Interface

Open the slave_interface_task.v. Recall, the slave_inferface is what sits in front of initiator (master) devices, interfacing it to the routing logic.

  1. Generate the BVALID and RVALID signals for when write responses and read data is ready to be transferred back to the connected initiator.
  2. Finish the logic to generate write packets to be sent to the appropriate responder through the routing logic.
  3. Complete the “re-order” logic for read data responses that come back to this device that may potentially be out of order and need to be written to our re-order buffer/table (Rdbuff) at the correct location.
  4. Finish the logic for the appropriate bookkeeping updates related to committing/popping the read data re-order buffer, Rdbuff.
  5. Finish the logic for determining which entry of the write response re-order buffer should be updated when a write response returns to the intiator.
  6. Finish the logic for the appropriate bookkeeping updates related to committing/popping the read data re-order buffer, Wrbuff.
  7. Finish the logic for the M2R_fifo read and write enables.

Task 1b - Responder Interface

Open the master_interface_task.v. Recall, the master_inferface is what sits in front of responder (slave) devices, interfacing it to the routing logic.

  1. The routing logic will need to deposit data into this device via the R2S_FIFO. Complete the logic for the S_put (write enable) signal for when the router should deposit new data into this FIFO and also for the S_get signal (read enable) for when the responder can pop data from the FIFO for processing and delivery to the responder device.
  2. For write transactions, you’ll need to store the appropriate bits in the appropriate re-order buffer, effectively demultiplexing the incoming write address or data to the appropriate table and entry.
  3. Lastly, write the appropriate muxing code to select the appropriate table entry to the write outputs to the responder.

Task 2: Simulate your design

  1. Start Model/Questasim.
  2. You do NOT need to create a project, but use the File..Change Directory option and navigate and choose the corresponding sim subfolder of your AXI lab directory
  3. At the Questasim prompt, type: source run.tcl
  4. This will compile and run the testbench to generate and log read and write requests and their responses. This information is saved to certain log files in the sim/results folder, which we then compare against expected (“golden”) versions which you can find in the sim/golden folder.
  5. If the results match the golden result, it will print a congratulatory Matching Output message/info. Otherwise, it will print the error info and you will need to debug your code use the simulation waveforms, etc.

NOTE 1: You can ignore the warnings such as:

# ** Warning: (vsim-3722) ./sources/router.v(150): [TFMPC] - Missing connection for port 'empty'.
# ** Warning: (vsim-3722) ./sources/router.v(150): [TFMPC] - Missing connection for port 'full'.
# ** Warning: (vsim-3722) ./sources/router.v(150): [TFMPC] - Missing connection for port 'one_location'.
# ** Warning: (vsim-3017) ./sources/router.v(173): [TFMPC] - Too few port connections. Expected 11, found 8.

NOTE 2: Some versions of Questasim and Modelsim format the output_memory.dump files differently. Older versions may write “001” instead of “1” for the address, and this causes a mismatch with the golden files. If this happens, please use the the four golden_output_memory.dump files in your sim/golden/pre-qsim folder with the files in the sim/golden folder.

Submission

submit -user ee560 -tag axi-lab slave_interface_task.v master_interface_task.v names.txt