EE 560 - Summer 2025 Digital Systems Design

Overivew

This lab has 2 parts:

  1. CPU with BRAM
  2. FIFO with BRAM

Task 1: CPU w/ BRAM

See subfolder Labs/Lab03/cpu-bram.

Prelab

Procedure

  1. Download and extract the source files lab03-cpu-bram.zip.
  2. Go through the complete bram0-noreg (Register Array-based memory implementation) design in src/des/bram0-noreg/cpu_5stage_NOREG.vhd. This is the baseline design that you will then update to use a flow-through (input register) or pipelined (input and output register) synchronous SRAM for the instruction and data memory.
  3. Other complete files that will be used in this design include ALU.vhd, dmem_NOREG_r1.vhd (data memory), Imem_NOREG.vhd (instruction memory), and reg_file.vhd (register file).
  4. The testbench files in src/tb are COMMON for all 3 designs and are COMPLETE. They include the main testbench cpu_tb.vhd, a package for reverse-translation of the machine code to assmebler, and then SIX instruction sequences in the i_fetch_test_stream_*.vhd files. Our .do scripts will run all SIX sequences through the testbench, capturing your data memory and register file results and ensure they match the expected, golden output in the sim/golden-results folder.
    • Note: only one instruction stream package file should be added to the project at the same time. But you don’t need to worry about this when you do behavioral simulations (sim/bram*/cpu_lab.do file will automatically place only one instruction stream package file at a time). However, you have to manually include only one instruction stream package file in your Xilinx project when you do post-route simulations
  5. Make a Questa/Modelsim simulation project in the sim/bram0-noreg folder. You do not have to add any sources manually as our cpu_lab.do file will compile the correct files and simulate the various instructions stream. It will also run a TCL script to automatically the compare the memory and register file results from each stream with out expected golden-results versions. (See the prelab to install TCL.)
  6. Run the cpu_lab.do script. It will take a while to run all 6 simulations. At the end you should inspect the results.txt file in your sim/bram0-noreg folder. It will indicated which traces failed or passed. If you passed all sequences you should see: Result is correct! in the file.
  7. For the first exercise (bram0-noreg), there should not be any difference between your result files and golden result files, since the design is complete. But for the remaining exercises, if one or more instruction sequences fail, you may comment out all the commands in cpu_lab.do that pertain to other stream sequences and simulate one sequence at a time (this will be clear if you look at cpu_lab.do) to debug your work.
  8. Now study the almost-complete design in src/des/bram1-ft/cpu_5stage_IREG.vhd, which uses a flow-through BRAM (i.e. an input register), and determine which signals you must connect to the indicated locations. Do not just guess but think carefully based on our discussion in lecture. When you think you have your design finished, create a new project in the sim/bram1-ft folder and run the cpu_lab.do file in that folder. Follow the procedure described above for bram0-noreg to check if your simulation passed and debug as necessary until all instructions sequences pass.
  9. Repeat the process for the almost-complete design in src/des/bram2-pipe/cpu_5stage_IOREG.vhd, which uses a pipelined BRAM (i.e. an input AND output register), and determine which signals you must connect to the indicated locations. Do not just guess but think carefully based on our discussion in lecture. When you think you have your design finished, create a new project in the sim/bram2-nopipe folder and run the cpu_lab.do file in that folder. Follow the procedure described above for bram0-noreg to check if your simulation passed and debug as necessary until all instructions sequences pass.
  10. Lastly, we want to ensure the code we’ve written is synthesizable. Follow the guidelines and procedures in the CPU-BRAM-PostSynthesisSimulationTask.pdf document in our shared folder to synthesize and simulate your design in Xilinx.
  11. Answer the questions in the cpu_bram_questions_su2021.pdf and submit the resulting annotated or exported PDF to Gradescope.

Submission

submit -user ee560 -tag cpu-bram1 cpu_5stage_IREG.vhd  names.txt
submit -user ee560 -tag cpu-bram2 cpu_5stage_IOREG.vhd names.txt

Task 2: FIFO w/ BRAM

See subfolder Labs/Lab03/fifo-bram-pipe.

Prelab

Procedure

In this task you will complete a 2-clock FIFO using a pipelined (input and output register) BRAM. You will NOT need to implement the design for an flow-through BRAM.

  1. Download and extract the source files lab03-fifo-bram-pipe.zip.
  2. Open and complete the missing parts (specified by the Task and TODO comments in the source code) in fifo_bram_ip_op_reg.vhd file.
  3. Inspect the testbench files in src/tb and especially the producer.vhd and its associated input file in the sim/ee560_producer_data.txt file. The producer side data file has 2 columns the first one is the producer side latency and the second one is the data to send out. The last three bits of the 16-bit data indicate consumer latency (suggesting the consumer to take a certain number of clocks to consume the provided data). Please do go through them to understand how producer and consumer latencies are emulated to simulate the environment external to the FIFO.
  4. Simulate your design by creating a project in the sim folder and then using the fifo_bram_ip_op_reg.do file. Compare your results produced in ee560_received_data.txt to ee560_received_data_golden.txt and similarly betwen ee560_sent_data.txt and ee560_sent_data_golden.txt. Debug your design if these do not match until they do.

Submission

submit -user ee560 -tag fifo_bram_ip_op_reg  fifo_bram_ip_op_reg.vhd  names.txt

Celebrate your success!