EE 560 - Summer 2024 Digital Systems Design

Overivew

This lab has 4-parts:

1. FPGA File I/O
2. Divider with Cache
3. Chipscope Lab
4. Gray-code counter

Task 1: File I/O - UART Assistant

See subfolder Labs/Lab02/FileIO-UART.

Prelab

• You can watch the linked File_IO_with_UART.mp4 video (recording date: 5/29/2022).
• Review the File_IO_with_UART_protocol_2020.pdf document regarding serial (UART) communications and how our FPGA based UART transmitter/receiver works.

Procedure

1. Start by reading the uartAssistant_Install_Megatest_2024.pdf document fully to get an overview.
2. For Windows users: Install the uARTAssistant tool that is in the UARTAssistantInstall subfolder linked on the shared folder. Follow the instruction in the uartAssistant User Guide.pdf in that subfolder. Note: Windows may flag this setup program as “not trusted”. Install it anyways.
3. For non-Windows users: You will need to run the tool via the VDI.
4. Download and extract the Conatenation_FileIO_2024.zip file which has a fully complete Vivado project for the concatenation_mem_3_A& exercise.
5. Follow the directions in the Concatenate_FileIO_ReadMe.pdf to run the mem_3_A7 exercise, going slowly to ensure you do not miss a step. Note: If you are trying to use the provide project in a newer version of Vivado, say yes to the various prompts to upgrade the project to a new folder structure and version of Vivado.
6. Continue to follow the instructions to create a new Vivado project for the mem_8_A7 exercise and ensure you can run the uARTAssistant tool successfully.
7. Demo this to your TA.
8. Answer the questions in the Assignment_FILE_IO_2021.pdf/docx and submit the resulting annotated or exported PDF to Gradescope.

Submission

• Demo your working mem_8_A7 project and the ability to run uARTAssistant to your TA.
• Review question: Individually complete and submit your annotated or exported PDF answers in the Assignment_FILE_IO_2021.pdf via Gradescope (also linked via D2L..Lab-Review-Submission module).

Task 2: Divider with Cache (Part 1 only)

All source code and background files are located in the Google Folder under the appropriate lab folder.

See subfolder Labs/Lab02/DivCache.

For this assignment, you only need to complete Part 1 described in the writeup and this should be done in your team of 2. Also, beware that some filenames may have changed, but the changes should be self-explanatory. You only need to modify two files: cam_generic.vhd and lru_generic.vhd.

Prelab

Review the CAM Lecture slides and lecture recording on D2L.

Procedure

1. Go through the assignment EE560_divider_with_cache_su24.pdf. There are a few changes to beware of:
2. You only need to do part 1.
3. We have already updated the “top” files, so no change is necesssary there.
4. We refer to the uART Assistant to send and receive data to the FPGA for input/output. This is covered in part 3 of the lab.
5. Submission of the answers to the questions at the end of the document should be made on Gradescope.
6. The file paths (folder structure) has been updated so you do not need to use paths like: C:\xilinx_projects\divider_with_cache.
7. Use the updated submission instructions that are provided on this website (i.e. this website supercedes the PDF documentation for submission.)
8. Download the source files.
9. This semester we are using the Artix-A7 boards. The .zip file below contains the source VHDL files for the divider with cache design, simulation/testbench files, a top-level, FPGA design with supporting files for uART Assistant as well as .xdc files, and solution/TA .bit files.
10. Complete tasks 1-3 described in cam_generic.vhd
11. Complete tasks 4-5 described in lru_generic.vhd.
12. Simulate the design by creating a simulation project in the sim folder and utilize the provided .do files. Iterate on your design until it simulates correctly.
13. In Vivado, create a Xilinx project in the syn folder and utilize the appropriate fpga and des files as well as the .xdc file for the A7 board.
14. In Vivado, use the Hardware Manager toownload the TA’s .bit file on to the board and make sure the design behaves using the UART Assistant.
15. Then, download your .bit file and ensure the behavior is similar. Demo this behavior to the course staff to get full credit.
16. Use the uARTAssistant tool to send data values to your FPGA and then use btnL and btnU (holding it down) to start and then step through the operation of the design as outlined in the PDF writeup.
17. Answer the questions on the last two pages using the parts of this lab using the EE560_divider_with_cache_su24_extract.pdf. You will submit this on Gradescope. This step is an INDIVIDUAL paper-submission task.

Submission

• Online Submission: Submit the following files
  • cam_generic.vhd (from src/des folder)
  • lru_generic.vhd (from src/des folder)
  • div_cache_results.vhd (from sim folder…produced by your simulation)
  • names.txt

submit -user ee560 -tag div-cache-p1 cam_generic.vhd lru_generic.vhd div_cache_results.txt names.txt

• Demo your working project and the ability to run uARTAssistant to your TA.
• Review questions: Individually complete and submit your annotated or scanned answers in the EE560_divider_with_cache_su24_extract.pdf via Gradescope (also linked via D2L..Lab-Review-Submission module).

Task 3: Chipscope

See subfolder Labs/Lab02/Chipscope.

• Individual-only lab (NO TEAMS).
• This is a paper submission only lab (no demo or code submission).

Prelab

• You can watch the linked Chipscope_Detour_Lab_Recording.mp4 video .
• Review the three HP and Xilinx reference documents provided in the shared folder:
  • HP_logic_analyzer.pdf
  • pg172-ila.pdf
  • ug936-vivado-tutorial-programming-debugging.pdf
• Review the lab presentation: Chipscope_intro_2020.pdf and supplemental material (Chipscope_Intro_Part1_r4_supplement.pdf) in the shared folder.

Procedure

1. Download the source files (cscope_detour_trigger.zip) in the shared folder.
2. Please make sure to understand the Chipscope instantiation workflow and try it on the FPGA board. The completed demo design has the .tsm file (trigger state machine) detour_sw1_sw2_sw3.tsm specifying a trigger of: SW1 ON - SW1 OFF - SW2 ON - SW2 OFF - SW3 ON - SW3 OFF.
3. Make a copy of this .tsm file with the name detour_sw1_sw2_sw3_sol.tsm and revise the trigger state machine to specify a trigger of: SW1 ON - SW2 ON - SW3 ON - SW1 OFF - SW2 OFF - SW3 OFF.
4. Run the ILA for a left (note left) detour signal with the new trigger state machine and capture the resulting waveform.
5. Complete the paper submission (lab02-cscope-detour-questions.pdf/docx) and include a snip of the waveform in your PDF report.

Submission

• Review question: Individually complete and submit your annotated or exported PDF answers in the lab02-cscope-detour-questions.pdf via Gradescope (also linked via D2L..Lab-Review-Submission module).

Task 4: Gray Code Counter

All source code and background files are located in the Google Folder under the appropriate lab folder.

See subfolder Labs/Lab02/GrayCode.

This lab may be done in teams.

You will use Verilog to build a 7-bit Gray code counter by cascading a less significant 3-bit Gray code counter to a more significant 4-bit Gray code counter. You only need to modify the 3-bit counter.

This lab is easy to complete, but there is a lot to learn to prepare for a question on the midterm exam!

Prelab

Review the Gray Code Lecture slides and lecture recording on D2L (as part of FIFO w/ BRAM topic).

Procedure

1. Download the source files: lab2-gray-cntr.zip
2. You only need to finish the TODO parts in gray-cntr3.v The other files are already complete.
3. Create a simulation project in the sim folder and use the given gray-cntr7-tb.do
4. If you get the following in your transcript window you have finished this lab and can celebrate!

#    
#  1745.00 ns   Gray Counter is at 127 now. Clk_cnt = 174 
#
#    Congratulations. No errors until now. 
#  

Submission

• Online Submission: Submit the following files
  • gray-cntr3.v (from src/des folder)
  • names.txt

submit -user ee560 -tag gray-cntr gray-cntr3.v names.txt