EE 560 - Summer 2024 Digital Systems Design

Divider - Debouncing and Single-Stepping

All source code and background files are located in the Google Folder under the appropriate lab folder.

See subfolder Labs/Lab01/VHDL/Divider.

For this assignment, Steps 1 through 6 below can be done individually or together with your lab partner, but Step 7 must be done as an INDIVIDUAL paper-submission.

Prelab

• Watch the Debouncing_SingleStepping.mp4 for a detailed overview by Prof. Puvvada ..or..
• Watch the prerecorded TA explanation video Lab1.mp4 video (please note that at various parts the TA did not share their whole screen and was referencing Vivado even though it was not appearing in the recording). Focus on the following time windows:
  • Start from 19:55 for overview of debouncing and single-stepping.
  • For explanations of the state diagrams start at 26:15 - 31:45

Procedure

1. Go through the assignment EE560_divider_su2017.pdf.
2. Download the source files.
3. This semester we are using the Artix-A7 boards. The .zip file below contains the source VHDL files, .xdc files, and solution/TA .bit files.
4. Go through the code in ee560_div_p1_simple,the src/div_mealy.vhd, tb/divider_mealy_tb.vhd, and src/fpga/div_top.vhd in the folder.
5. Download the TA’s .bit file on to the board and make sure the design behaves (single stepping, etc.)
6. Now using the source files (.vhd and .xdc) to set up Xilinx project for EACH of the 3 parts and synthesize and implement each of the three designs to get practice.
7. Answer the questions on the three parts of this lab using the EE560_divider_su2017_extract_for_submission.pdf. This step is an INDIVIDUAL paper-submission task.

Submission procedure

Paper submissions are to be done INDIVIDUALLY and should be submitted on the course Gradescope site (also linked via D2L..Lab-Review-Submission module).

Demo submission

Please demo your synthesized part 3 running on the FPGA to your TA before the due date.

Timing Constraints - Not Assigned For Su24

See subfolder Labs/Lab01/VHDL/Timing. (Note: this is not assigned in Su24)

Procedure

1. Download the file timing_constraints_su19.zip and extract the files
2. Download the Timing_constraints_paper_submission.pdf and timing_constraints_su19.pdf documents.
3. As a reference, review ee354l_timing.pdf, from the EE354L lab on timing to discuss about loop unrolling.

Update from 2023 and Onward: There is some confusion regarding part 4 of the Timing constraints lab and we apologize for the same. Our assignment pdf file does not say certain things but the solution on the ee560 class account assumes those things. So, we want to clarify. The server solution assumes that you have a “for” loop such a way that you have at least 4 subtractors or more and it allows you to compare X with 4Y or 2Y besides with Y. By the way, comparing with 2Y or 4Y is easy.Instead of writing if (x <= 4*Y), you can write if ("00" & x <= y & "00"). In VHDL, & means concatenate.

Also note that we can exit from the Compute state to the Done state at the end of the first clock if (X < Y), since

• (i) we know that we will not be changing X or Q when X is less than Y, and
• (ii) the update logic (for updating X and Q) will not try to update X and Q anyway at the end of the first clock, so we do not care about the fact that the combinational logic in the data-path (namely the cascaded subtractors) is long and has not produced stable output results.

In our assignment, on the last page in sec 6.3, we wrote, “You also need to revise the core design to stay for two clocks in compute state at a stretch whenever at least one subtraction operation is successful”. Based on the above high-lighted part, we expect students to conclude that whenever X is less than Y, they can exit to Done state without checking for the second clock.

Hope the above helps!

Online Submission

submit -user ee560 -tag divider_timing divider_timing_part2.vhd divider_timing_part3.vhd divider_timing_part4.vhd divider_timing.xdc names.txt

Paper submission

Paper submissions are to be done INDIVIDUALLY and should be submitted on the course Gradescope site (also linked via D2L..Lab-Review-Submission module).