EE 560 - Summer 2025 Digital Systems Design

Divider - Debouncing and Single-Stepping

All source code and background files are located in the Google Folder under the appropriate lab folder.

See subfolder Labs/Lab01/VHDL/Divider.

For this assignment, Steps 1 through 6 below can be done individually or together with your lab partner, but Step 7 must be done as an INDIVIDUAL paper-submission.

Prelab

• Watch the Debouncing_SingleStepping.mp4 for a detailed overview by Prof. Puvvada ..or..
• Watch the prerecorded TA explanation video Lab1.mp4 video (please note that at various parts the TA did not share their whole screen and was referencing Vivado even though it was not appearing in the recording). Focus on the following time windows:
  • Start from 19:55 for overview of debouncing and single-stepping.
  • For explanations of the state diagrams start at 26:15 - 31:45

Procedure

1. Go through the assignment EE560_divider_su2017.pdf.
2. Download the source files.
3. This semester we are using the Artix-A7 boards. The .zip file below contains the source VHDL files, .xdc files, and solution/TA .bit files.
4. Go through the code in ee560_div_p1_simple,the src/div_mealy.vhd, tb/divider_mealy_tb.vhd, and src/fpga/div_top.vhd in the folder.
5. Download the TA’s .bit file on to the board and make sure the design behaves (single stepping, etc.)
6. Now using the source files (.vhd and .xdc) to set up Xilinx project for EACH of the 3 parts and synthesize and implement each of the three designs to get practice.
7. Answer the questions on the three parts of this lab using the EE560_divider_su2017_extract_for_submission.pdf. This step is an INDIVIDUAL paper-submission task.

Submission procedure

Paper submissions are to be done INDIVIDUALLY and should be submitted on the course Gradescope site (also linked via D2L..Lab-Review-Submission module).

Demo submission

No demo is required for this lab, but you should ensure you can correctly single-step through the division process on the FPGA board.

Timing Constraints - Not Assigned

See subfolder Labs/Lab01/VHDL/Timing. (Note: this is not assigned this semester)