EE 560 - Summer 2025 Digital Systems Design

RTL Coding in VHDL

This portion of the lab consists of 3 parts:

  1. Parity Generator
  2. Special Counter
  3. Yards-Feet-Inches Converter

RTL coding in VHDL - Parity Generator

All source code and background files are located in the Google Folder under the appropriate lab folder.

See subfolder Labs/Lab01/VHDL/Parity.

Description

A(n) (odd) parity generator gives a high output if the input data has an odd number of 1’s and a low output if the input has an even number of 1’s. So, this is a simple combinational XOR function of all the bits of the input. This can easily be described in HDL using a for loop in a combinational process. You know that the for loop is unrolled by the synthesis tool. You also know that the for loop in a combinational process does not imply any hardware iteration like in a serial parity generator. In VHDL, the parity value should be a variable declared in the process, and not a signal declared in the architecture. It should be initialized to zero and it is XOR’ed with every bit of the input (one bit per iteration) and hence, after the for loop is executed, it is effectively the xor of all the bits of the input.

Procedure

  1. Go through parity.v and understand the design
  2. Run the Simulation tool (e.g. Modelsim, Questasim, etc) using the testbench file parity_tb.v and verify the result by reading messages in the transcript panel.
  3. Make a file parity_vhdl.vhd by converting parity.v to VHDL. parity_vhdl.vhd should have an entity named parity_vhdl and should have a 32-bit input called in_data and an 1-bit output, parity. Please make sure to follow this naming convention otherwise it will not be compatible with the given VHDL testbench file parity_vhdl_tb.vhd. Our grading scripts on Unix also use these names.
  4. Now repeat simulation, but this time with the VHDL version, parity_vhdl.vhd and parity_vhdl_tb.vhd and verify the result.

Online Submission

submit -user ee560 -tag parity parity_vhdl.vhd names.txt

Ensure you:

RTL coding in VHDL - Special Counter

All source code and background files are located in the Google Folder under the appropriate lab folder.

See subfolder Labs/Lab01/VHDL/Special-Counter.

Prelab

Review pages 101 and 102 of the document EE201L_counters_blocking_non_blocking_r1.pdf in the shared folder. You can also review EE201L_Special_counter_blocking_non_blocking_r1.pdf.

Procedure

Review the skeleton files provided:

Make a simulation project in the sim/vlg folder, add the source files (design and testbench) – but avoid copies, just reference the given source files by adding “existing” items – and simulate the design using the .do files. You can reference the EE457_ModelSim_PE_Testing_USC.pdf file in the Lab01/VHDL folder for a general walk through of how to setup a simulation project, though you don’t need to run through the actual example. Just use it as a guide for how to do the similar work with this codebase.

In this lab, we’re going to use .do files so please type the following command in the ModelSim transcript panel after you make a project and start simulation.

do special-cntr-vlg.do

Then, analyze the output file special-cntr-results-vlg.txt and verify your understanding of this special counter.

Online Submission

FTP the appropriate individual vhdl files to your UNIX account and submit them online to the ee560 class account using the following unix command:

submit -user ee560 -tag special-cntr special-cntr.vhd special-cntr-tb.vhd special-cntr-results-vhdl.txt names.txt

Ensure you:

RTL coding in VHDL - Convert Inches to Yards-Feet-Inches

All source code and background files are located in the Google Folder under the appropriate lab folder.

See subfolder Labs/Lab01/VHDL/Yards-Feet-Inches.

Prelab

Before coming to lab, please go through the documents in the Google folder related to the Moore Machine question and solution for the Inches => Feet => Yards conversion

Procedure

entity yard_feet_inches is
port(
    -- inputs
    inches_in   : in    std_logic_vector(7 downto 0); -- inches
    start       : in    std_logic;
    ack         : in    std_logic;
    -- outputs
    done        : out   std_logic;
    inches_out  : out   std_logic_vector(7 downto 0); 
    feet_out    : out   std_logic_vector(7 downto 0);
    yards_out   : out   std_logic_vector(7 downto 0);
    -- clock and reset
    resetb    : in    std_logic;
    clk       : in    std_logic
);
end yard_feet_inches ;

Online Submission

FTP the appropriate individual files to your UNIX account and submit them online to the ee560 class account using the following unix command:

submit -user ee560 -tag yfi  yfi.vhd  yfi_output_actual.txt names.txt

Ensure you: