Prof. Redekopp’s Verilog Tutorial
Below are Prof. Redekopp’s Verilog tutorial notes and accompanying videos.
Notes: PDF
Videos:
- 1 - Intro : Recommend everyone watch.
- 2 - Verilog Basics: Optional. Can skip if you have learned some Verilog before.
- 3 - Timing and Simulation: Recommended, but can skip if you have learned some Verilog before.
- 4 - Verilog Intermediate (Easy Mistakes): Everyone should watch.
- 5 - Design Tips: Everyone should watch.
Basic RTL design:
You may need to find a video player that supports .avi and .wmv formats. For Windows, this application should suffice.
- DPU and CU
- Mealy machine example – Divider Design
- Data registers – clocking and controlling
- Loop Counter Incrementation and Terminal Value Checking
- ME (Mutually Exclusive) and AI (All Inclusive) rules in designing a state diagram
- State diagram Design examples
Verilog Learning Modules
Verilog HDL:
Six lectures (together with slides) were posted at the link below to introduce the essential aspects of Verilog to the EE354L students (and to the graduate students in EE457, who are new to Verilog coding), so that they can get started with using Verilog for completing their labs. The lectures add up to 3 Hours 40 minutes.
Individual links
1_Verilog_Introduction_mht.jnt
1_Verilog_Introduction.avi (1 H 08 Minutes)
2_module_DataTypes_in_Verilog.jnt
2_module_DataTypes_in_Verilog.avi (23 minutes)
3_behavioral_vs_structural_Verilog.jnt
3_behavioral_vs_structural_Verilog.avi (17 minutes)
4_Sequential_Statements_in_Verilog.jnt
4_Sequential_Statements_in_Verilog.avi (1 Hour)
5_blocking_non_blocking.avi (56 minutes)
6_RTL_coding_style.avi (33 minutes)