MT Info
Overview and Process
- Time/Date: 1 p.m., Fri. June 20th
- Location: SLH 100
- The test will be set for 2 hours
- If you have USC approved accommodations, please confirm with me via email and we will make preparations for your approved time.
- The test will be taken as a paper/pen exam.
- The exam is Closed book, Closed notes, Closed Internet (search/reference). You may use your mind and blank scratch paper but nothing else. No referencing your labs, homeworks, etc.
Topics and Style
The exam will include a mix questions over the topics listed below and be similar to the HW problems and/or lab questions. Thus, most questions will not be simple memory / factual questions but instead test the depth of your ability to use relevant course concepts to analyze and design new problems.
Unit 1a - Digital Design Review
- Datapath design: adders, muxes, registers (w/ enables), counters, memories
- Control Unit design: 1-hot FSM design, Mealy vs. Moore outputs
Unit 1b - Fixed Point Arithmetic Review
- Binary representation in unsigned and signed (2’s complement)
- Signed and zero extension
- Addition and subtraction in unsigned and 2’s complement
- Overflow tests for unsigned and signed addition and subtraction
- Basic ALU design
Unit 2 - ISA
- General concepts of instruction sets (instruction format, registers, addressing modes), RISC vs. CISC
- MIPS instructions: ALU/R-Type, immediate, Load/Store, Branch, Jump,
jal,jr, instructions - Comparison with SLT and
beq/bne - Limitations of branch displacements and jump addresses
- System stack usage conventions
- Function call and usage of the stack (pre- and post-amble sequence of functions)
Unit 3 - Performance
- Fallacies and pitfalls of using rates
- (“Iron Law”) Performance equation: (Time = IC * CPI * Period)
- Calculating average CPI
- Amdahl’s law and implications for improving the common case
Unit 4 - Arithmetic
- Ripple carry adders
- Carry-lookahead adders design
Unit 5 - Single-Cycle CPU
- Single-cycle CPU components and datapath
- Single-cycle control unit implementation approach
- Updating the datapath/control unit to support additional instructions (similar to HW5)
Unit 6 - Pipelining
- Basic concepts (ideal speedup, challenges to attaining the ideal speedup)
- Conversion of single-cycle CPU to 5-stage pipeline
- Control logic and control signal generation on the 5-stage pipeline
- Data hazards (what are they, how can they be solved with the HDU or Forwarding Unit, when is stalling required (i.e. forwarding cannot solve) for a general pipeline)
- Control hazards (what are they, flush mechanism, mitigating with early vs. late determination, use of delay slots, etc.)