Final Info
Overview and Process
- Time/Date: 8:30 a.m., Tues. July 15th
- Location: OHE 122
- The test will be set for 2 hours.
- If you have USC approved accommodations, please confirm with me via email and we will make preparations for your approved time.
- The test will be a paper/pen exam.
- The exam is Closed book, Closed notes, Closed Internet (search/reference). You may use your mind and blank scratch paper but nothing else. No referencing your labs, homeworks, etc.
Topics and Style
The exam will include a mix questions over the topics listed below and be similar to the HW problems and/or lab questions. Thus, most questions will not be simple memory / factual questions but instead test the depth of your ability to use relevant course concepts to analyze and design new problems.
Unit 7 - Memory Hierarchy
- Caching
- Policies and basic approach
- Mapping schemes and their implementation
- Hierarchy of multiple levels, principle of inclusion, etc.
- Main Memory organization
- Interleaving / banking
- DRAM vs. SRAM
- Latency vs. throughput
- Virtual memory
- Approach and basic definitions
- Address translation using (1 or more levels of) page tables
- Speeding translation with TLBs
- Page fault processing (ensuring appropriate data is removed from and/or updated in appropriate structures)
- Cache Coherence
- Snooping-based protocols: MSI, MESI, etc.
- Scalability and need for directory based protocols
Unit 8 - Exceptions
- Kinds and types
- Handling in a pipelined system (temporal vs. program order)
Unit 9 - Parallelism
- Instruction level parallelism
- Static vs. dynamic scheduling
- Tomasulo’s algorithm for out-of-order execution (basic operation, use of tags and the CDB, handling WAR and WAW hazards, tag generation)
- Speculative execution with the ROB and its benefits
- Handling Load / Store ordering
- Thread level parallelism
- Limits of ILP and how TLP can overcome those
- Types (coarse-grained, fine-grained, simultaneous multithreading)
- Data Level Parallelism (SIMD)