EE457 - Summer 2025 Computer Systems Organization

Lab 2

See Assignments Page

Materials

See the the Labs..Lab2 subdirectory of the Shared folder

• Handout:: Read PDF the handout
• Skeleton Files: Download the skeleton file and testbench file in the provided .zip file which contains:
  • src/des/ee457_alu.v contains a partially complete ALU design. Do not modify the port interfaces but feel free to add additional internal signal declarations and your behavioral/RTL description.
  • src/tb/ee457_alu_tb.v contains a complete testbench to test SOME cases but is definitely NOT a definitive test that ensures your FIFO has 0 bugs.
  • sim folder contains a .do file that you can use to compile and simulate your design in Questasim. It expects you have used the File..Change Directory command to point to that sim folder as all references in the .do file are relative to that folder.

Procedure

In teams of 2:

• Follow the instructions in the handout.

• Complete the ALU design, simulating, and verifying it using the provided testbench. The testbench has many test cases for various modes and overflow scenario, but is not exhaustive. Read it carefully to understand the inputs and expected values.

Submission

• Create a file with the name of you and your partner in a file names.txt.
• Also submit the following files:
  • ee457_alu.v
  • ee457_alu_tb.v
  • names.txt
• Zip all your files (all Verilog design and testbenches as well as the program and data .txt files) in a a SINGLE .ZIP file (not .bz2, not .gz, not .tar but zip) named lab2.zip.
• Submit your .ZIP file on the EE 457 Brightspace site in the Lab 2 dropbox under the Labs.