EE457 – Lab 2

Lab 2

See Assignments Page

See the the Labs..Lab2 subdirectory of the Shared folder

Handout:: Read PDF the handout
Skeleton Files: Download the skeleton file and testbench file in the provided .zip file which contains:
- src/des/ee457_alu.v contains a partially complete ALU design. Do not modify the port interfaces but feel free to add additional internal signal declarations and your behavioral/RTL description.
- src/tb/ee457_alu_tb.v contains a complete testbench to test SOME cases but is definitely NOT a definitive test that ensures your FIFO has 0 bugs.
- sim folder contains a .do file that you can use to compile and simulate your design in Questasim. It expects you have used the File..Change Directory command to point to that sim folder as all references in the .do file are relative to that folder.

In teams of 2:

Follow the instructions in the handout.
Complete the ALU design, simulating, and verifying it using the provided testbench. The testbench has many test cases for various modes and overflow scenario, but is not exhaustive. Read it carefully to understand the inputs and expected values.

EACH (BOTH) TEAM MEMBER should submit their code (though it will obviously be the same for both)
Login to EdStem and go to Lessons..Lab2a - ALU and the SIMD ALU slide.
Replace the contents of ee457_alu.v with your code (either by copy/paste of the entire contents or by uploading and replacing the skeleton file with your own.)
Run the Test button at the bottom
Once it passes, click Submit.