Lab 1
See Assignments Page
Materials
See the the Labs..Lab1 subdirectory of the Shared folder
- Handout:: Read PDF the handout
- Skeleton Files: Download the skeleton files and testbench file in the provided
.zipfile which contains an almost complete 5-stage pipelined CPU that you will complete.
Procedure
In teams of 2:
- Complete all 6 state diagrams
- Complete the Verilog implementation and testing for only Part 1, Part 3 Method 1, Part 3 and Method 3 but each individual should submit their own copy of these files.
If you are working on your Unix account you can extract the files and then FTP them to your aludra account via FileZilla or other SFTP tool available from USC.
Individually
- Answer Questions 1 and 2 ( answers should be unique for every individual…don’t work in groups )
Submission
Submit your code as a SINGLE .ZIP file (not .bz2, not .gz, not .tar but zip) with the following files. You can do an Internet search to see about how to create a zip file from the command line or with 3rd party tools like 7-Zip. Submit your .ZIP file on the EE 457 Brightspace site in the Lab 1 dropbox under the Labs.
min_max_finder_part1.voutput_results_part1.txtmin_max_finder_part3_M1.voutput_results_part3_M1.txtmin_max_finder_part3_M3.voutput_results_part3_M3.txtnames.txt(should contain the name of you and your lab partner).answers.pdf- should contain the answers/state diagrams for the individual questions- SCAN your state diagrams with a PDF app on your phone, if necessary. NO
answers.jpgor other pictures…
- SCAN your state diagrams with a PDF app on your phone, if necessary. NO