Lectures
Lecture Schedule
| Lec | Topic | Slides |
|---|---|---|
| 1 | Course Overview (Vahid Ch. 1) |
[PDF] |
| 2 | Combinational vs. Sequential, Overview of Clocking Methodologies, Design Goals; Logic Functions (Vahid: 2.6, 2.8) | [PDF Notes] [PDF Complete] |
| 3 | Boolean Algebra (Single variable), Decoders & Muxes (Vaid: 2.5-2.9) | [PDF Notes] [PDF Complete] |
| 4 | Minterms, Maxterms, Canonical Sums, Logic Function Synthesis using Boolean Algebra (Vahid: 2.7) | [PDF Notes] [PDF Complete] |
| 5 | Boolean Algebra, Structural Verilog (Vahid: 2.7, 9.2) | [PDF Notes] [PDF Complete] [Verilog Complete] |
| 6 | Logic Function Synthesis using Karnaugh Maps (Vahid: 6.2) | [PDF Notes] [PDF Complete] |
| 7 | More Karnaugh Maps, Registers, State Machines Design Overview (Vahid: 3.2, 4.2) | [Register PDF Notes] [Register PDF Complete] |
| 8 | State Machine Design (Vahid: 3.3-3.4) | [State Machines PDF Notes] [State Machines PDF Complete] |
| 9 | More State Machine Design (Vahid: 3.3-3.4); | |
| 10 | Transistor Switching Models; nMOS, pMOS, CMOS (Vahid: 2.1-2.4, Kang: Ch 2) | [PDF Notes] [PDF Complete] |
| 11 | More CMOS; Overview of fabrication process (Vahid: 3.3-3.4) | [ Previous slides (cont.) ] |
| 12 | Datapath Components (Adders and Counters) (Vahid: 4.3.-4.4, 4.9) | [PDF Notes] [PDF Complete] |
| 13 | Datapath Components (cont.) (Vahid: 4.3.-4.4, 4.9) | [PDF Notes] [PDF Complete] |
| 14 | Memories + Midterm Review | [PDF Continued] |
| Feb. 22 | Midterm during Quiz section (Feb. 22: 7-8:30 p.m. in Room TBA) | |
| 15 | Datapath Components (Fast Adders, Comparators, Memories) (Vahid: 4.6-4.7, 6.5) | [PDF Notes] [PDF Complete] |
| 16 | Negative Logic, One-hot State Machine Design, System Design Example: Multiplier (Vahid: 6.3) | [PDF Notes] [PDF Complete] |
| 17 | System Design Examples: Multiplier & Vending Machine | [PDF Continue] |
| 18 | More System Design | |
| Spring Break | ||
| 19 | Combinational synthesis with muxes & memories (Vahid: 2.5, 2.7) | [PDF Notes] [PDF Complete |
| 20 | Sequential components (Bistables, latches, FFs) (Vahid: 3.2, 4.9) | [PDF Notes] [PDF Complete] |
| 21 | MOS Theory (Kang, Ch. 3) | [PDF Notes] [PDF Complete] |
| 22 | Capacitance, Delay, and Sizing | [PDF Notes] [PDF Complete] |
| 23 | More Capacitance and Delay | |
| 24 | Layout Memory Cells & Sequential components (Kang, Ch. 10) |
[Layout PDF] [Memory Notes] [Memory Complete] |
| 25 | Memory Cells (cont.) | |
| 26 | ASIC vs. FPGA (Vahid: 7.1-7.3), Hardware/Software Interfacing, PicoBlaze | [PDF Notes] [PDF Complete] |
| 27 | Project Overview & More Interfacing | [cont.] |
| 28 | Examples | [PDF Notes/Complete] |
| 29 | Single-Cycle CPU | [PDF Notes] [PDF Complete] |
| 30 | Review | None |
| Final Project Due during Friday April 27th in Discussion | ||
| Final Exam (May 8th at 8 a.m.) |