EE209 - Spring 2018 Foundations of Digital System Design

Discussion/Lab

Discussion will be used to introduce lab and review important concepts from lecture. Be sure to attend.

Labs

All labs must be demoed in your registered lab 1 week after it is assigned unless otherwise noted. Reports and code files must be submitted by midnight of the Friday that the lab is demoed.

Video explanation
Lab Start Due Handout/Topic Files to Download Notes and Other Links Submission
01 1/12 1/19 Xilinx CAD Tools overview mux.v
mux4.v
mux4_tb.v
Follow the Xilinx setup instructions on your Windows PC or setup your Virtual Desktop Interface (VDI) and watch the Introductory video for learning to use the Xilinx design entry tool and simulation tools on the tools page. Demo to TA
02 1/19 1/26 Sound the Alarm alarm.zip - Project Skeleton None Demo to TA and submit files here
03 1/26 2/2 Mastermind Design mmind.zip Watch the video on hierarchical Verilog description. Then download the skeleton project and unzip (extract) it to a folder on your PC or VDI where you can work on it. Carefully read the handout to understand the overall design of the Mastermind game and what you need to do in this lab. We will be updating and modifying the majority of the skeleton components over the next lab or two. So do your best on this portion so you are ready for the subsequent lab. **Note:** The learning curve with this lab can be steep so please start early, invest time into it and ask questions. Demo to TA and submit files here
04 2/2 2/9 Mastermind Remix mmind_fsm.v Replace the old mmind_fsm.v file with the new version provided and then complete the logic in that file.
Use the worksheets at the back of the handout that include blank Karnaugh maps for the functions you will need to design.
Demo to TA and submit files here
05 2/9 2/16 Enter the Code seqdet.zip Enter the code into sequence detecting state machine!
Here is an video introduction to the lab.
Demo to TA & submit files here
06 2/16 3/2 We Value Your Feedback lfsr.zip Implement a Linear Feedback Shift Register (LFSR) to perform hardware based encryption and decryption of a data stream.
Here is a video explanation of this lab.
Demo to TA & submit files here
07 3/2 3/9 A Walk-Off cwalk.zip Implement a crosswalk controller. Demo to TA & submit files here
08 3/9 3/30 Change We Can Believe In vending.zip Implement a vending machine controller Demo to TA & submit files here
09 3/30 4/6 Range Finder ping.zip Implement a ultrasonic range finder controller Demo to TA & submit files here
10 4/6 4/20 Heap it On heap1.zip Build a HW-based priority queue (heap) controller Submit files here
11 4/20 5/1 Blaze of Glory heap2.zip Heap + Picoblaze SoC
Website to compile heap2.psm
PicoBlaze (KCPSM6) Documentation
Submit files here