# EE109 – Spring 2018: Introduction to Embedded Systems

## Lecture Schedule

The following is a tentative schedule for the Spring 2018 semester.

Week | Tuesday | Lab - Wednesday/Friday | Thursday |
---|---|---|---|

1 1/8-1/12 |
Orientation, embedded systems, computer organization [PDF Complete] First Day Survey |
Lab 0: Installing the Arduino Toolchain (Linux tutorial, software installation) | Basic circuit analysis (voltage, current, Ohm's law) ( Watch this video before coming to class))[PDF Notes] [PDF Complete] |

2 1/15-1/19 |
Circuits (LED, switches), digital circuits, transistors [PDF Notes] [PDF Complete] |
Lab 1 - Electronic circuits (exploration of KVL/KCL/Ohm's laws) | Digital logic, combinational and sequential circuits; Boolean Algebra [PDF Notes] [PDF Complete] |

3 1/22-1/26 |
Number systems, binary, hexadecimal, character codes [PDF Notes] [PDF Complete] |
Lab 2: Digital Logic - Gates (oscilliscopes, combinational gate network, delays) | Microcontollers 1 (bitwise operations) [PDF Notes] [PDF Complete] |

4 1/29-2/2 |
Microcontrollers 2 (digital I/O) | Lab 3: Digital Logic - Arduinos | Microcontroller 3 (advanced bit fiddling), state machines [PDF Notes] [PDF Complete] |

5 2/5-2/9 |
LCDs and parallel interfaces [PDF Notes] [PDF Complete] |
Lab 4: LCDs | Combinational logic design 1 (decoders and muxes) [PDF Notes] [PDF Complete] |

6 2/12-2/16 |
Combinational logic design 2 (minterms, canonical sums) [PDF Notes] [PDF Complete] |
Lab 5: Software State Machines (button debouncing) | Digital I/O QuizCombinational logic design 3 (2 & 3 variable Boolean algebra) |

7 2/19-2/23 |
Combinational logic design 4 (Karnaugh maps) [PDF Notes] [PDF Complete] |
Lab 6: ADCs | Combinational logic design 5 (Karnaugh Maps) |

8 2/26-3/2 |
Combinational logic design 6 (K-Maps & memories) | Open lab | Binary systems (signed), arithmetic [PDF Notes] [PDF Complete] |

2/28 | Midterm 1 in the Quiz Section[Midterm Info] |
||

9 3/5-3/9 |
Interrupts [Interrupt PDF Notes] [Interrupt PDF Complete] [Rotary Encoders PDF Complete] |
Lab 7: Interrupts | Combinational logic design 6 (adders) [PDF Notes] [PDF Complete] |

3/12-3/16 | Spring Break |
||

10 3/19-3/23 |
Sequential logic 1 (latches, FFs and registers) [PDF Notes] [PDF Complete] |
Lab 8: Timers [PDF Complete] |
Sequential logic 2 (latches, FFs and registers) [PDF Notes] [PDF Complete] |

11 3/26-3/30 |
Interfacing (voltage and current capabilities) [PDF Notes] [PDF Complete] |
Lab 9: Serial communications [PDF Complete] |
Hardware state machines 1 [PDF Notes] [PDF Complete] |

12 4/2-4/6 |
Hardware state machines 2 | Project | Computer organization 1 (ALUs, registers, instruction cycle) [PDF Notes] [PDF Complete] |

13 4/9-4/13 |
Computer organization 2 (instruction sets, assembly language) | Project Work | Processor Organization [PDF Notes] [PDF Complete] |

14 4/16-4/20 |
Performance (caching, pipelining) [PDF Notes] [PDF Complete] |
Project |
Hardware accelerators [PDF Notes] [PDF Complete] |

15 4/23-4/27 |
Midterm review, project work | Project | Project work EE 109 Post-Survey |

4/25 | Midterm 2 in the Quiz Section |
||

4/27 Friday |
Last Day to Demo Project |
||

5/9 Wednesday |
Last Day to Submit Project code on Vocareum |